A bit-serial floating-point unit for a massively parallel system on a chip
نویسندگان
چکیده
This paper presents the design of a new bit-serial floating-point unit (FPU). It has been developed for the processors of the Instruction Systolic Array parallel computer model. In contrast to conventional bit-parallel FPUs the bit-serial approach requires a different data format. Our FPU uses an IEEE compliant internal floating-point format that allows a fast least significant bit (LSB)-first arithmetic and can be efficiently implemented in hardware.
منابع مشابه
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عنوان ژورنال:
- Parallel Algorithms Appl.
دوره 19 شماره
صفحات -
تاریخ انتشار 2004